An energy-efficient V cm -based split capacitor switching scheme for high speed SAR ADCs

A V cm -based split capacitor switching scheme for high speed successive approximation register (SAR) analogue-to-digital converters (ADCs) is presented. By reducing the time constant of the bit cycles, the proposed technique achieves shortest settling time among the existing switching techniques. It also reduces total capacitance by 75% and switching energy by 93.7% compared with the conventional method. In addition, the impact of common-mode voltage (V cm ) accuracy on the proposed digital to analogue converter (DAC) is alleviated and the output common-mode voltage of the DAC remains almost stable during the whole conversion.