An MLP-aware leakage-free memory controller

Timing channels can be exploited to leak information between two virtual machines running on a shared server. Indeed, cache timing channels are important components in the Spectre attack. A shared memory controller can also be leveraged to establish a timing channel. Recent efforts have designed memory controllers that eliminate such timing channels, but that incur throughput penalties of over 2X. This paper advances the state-of-the-art by better matching the memory controller policies to the memory-level-parallelism (MLP) needs of typical applications. Our new memory controller improves upon the performance of the state-of-the-art policy by 14%, while eliminating memory controller timing channels.