Slew-Aware Buffer Insertion for Through-Silicon-Via-Based

Large parasitic capacitances of through-silicon-vias in 3D ICs cause signal slew and delay to increase. We propose a buffer insertion algorithm that further reduces delay by considering slew explicitly. Compared with the well-known van Ginneken algorithm and a commercial 2D tool, our algorithm improves full-chip timing with acceptable runtime overhead. I. INTRODUCTION For high performance 3D ICs, it is crucial to perform thorough timing optimization, especially when the 3D nets are on timing critical paths. Among timing optimization techniques, buffer insertion is known to be the most effective way. However, currently there is no commercial design software that performs buffer insertion on multiple die designs simultaneously. The through-silicon-vias (TSVs) provide 3D interconnects, yet the large parasitic capacitances of TSVs cause signal slew and delay to increase. In addition, the unit length resistance of wires in today's advanced technology nodes is very high, which causes slew degradation along nets and increases gate delay. Buffer insertions on large circuits became practical with the van Ginneken's dynamic programming (VGDP) (1). Then, the VGDP