Strain Controlled CMOSFET with Phase Controlled Full-Silicide (PC-FUSI)/HfSiON Gate Stack Structure for 45nm-node LSTP Devices

By using Ni-FUSI/HfSiON gate structure with NiSi electrode for NFET and Ni 3 Si for PFET, excellent T inv -I g property (T inv :1.8 nm , I g :7E-3 A/cm 2 ), symmetrical V th (+/-0.4V), high I on :510/270 muA/mum with I off : 100 pA/mum are achieved at L g :45nm. These properties are suitable for 45nm-node CMOSFET for LSTP. To introduce Ni 3 Si electrode for PFET, poly-Si gate electrode height optimization successfully overcomes volume expansion problem which causes Ni diffusion into Si substrate during full-silicidation process. For the precise thickness control of thin poly-Si electrode, we propose four-layered gate stack process. Channel strain measurement reveals that Ni 3 Si from thin poly-Si introduces compressive strain to channel, which increases the hole mobility. It is considered that the thermal expansion coefficient mismatch between Ni 3 Si and Si realizes the compressive stress compensating the tensile stress induced during silicidation. TEM observation shows connecting point between NiSi of NFET and Ni 3 Si of PFET has abrupt interface, which suggests phase controlled full-silicidation (PC-FUSI) process is suitable for the further scaling down of CMOSFET for LSTP