Efficient Variability- and Reliability-aware Device-Circuit Co-Design: From Trap Behaviors to Circuit Performance

An efficient variability- and reliability-aware methodology is proposed to achieve the device-circuit co-design and is demonstrated on Nanosheet (NS) FETs based circuits. The main features include: (i) The single trap impact mapping (STIM) method links the charge distributions to the time-dependent variability and reliability. (ii) A trap behavior-based 3D-Kinetic Monte Carlo simulator is developed to capture the statistical charge distributions in the gate dielectric under different stress conditions in the presence of time-zero variations. (iii) A database which includes ΔV th , ΔSS and its correlation under various device degradation probabilities (DP) and thermal stress ratios (TSR) is set up, significantly reducing the device simulation time. (iv) A variation-aware model based on the database is proposed to predict the time-dependent delay degradation and potential critical paths in the digital circuits coupled with self-heating at arbitrary operating conditions.