Capacitance Scaling in In 0.71 Ga 0.29 As/InP MOSFETs With Self-Aligned a:Si Spacers

In0.71Ga0.29As/InP (12/2 nm) quantum well MOSFETs using sacrificial amorphous silicon (a:Si) spacers to achieve low parasitic capacitance are fabricated. Radio frequency characterization of 73 devices is used to study the intrinsic and extrinsic capacitances. The total gate intrinsic parasitic capacitance of 0.55 fF/ $\mu \text{m}$ is achieved with an intrinsic gate capacitance of $0.39~\mu \text{F}$ /cm2. The various parasitic capacitances are modeled using finite element electrostatic simulations, and semi-analytical expressions are provided. A device with a gate length ${L}_{g}=80$ nm has SS $_{\text {min}}=168$ mV/dec, dc transconductance ${g}_{\textit {m,e}} =1.0$ mS/ $\mu \text{m}$ at ${V}_{\text {DS}}=0.5$ V, and exhibits a peak cutoff frequency $\it f_{\!{T}} $ of 243 GHz, and a maximum oscillation frequency $\it f_{\text {max}}$ of 147 GHz at ${V}_{\text {GS}}=0.25$ V, ${V}_{\text {DS}}= {1}$ V.