Controller Architecture for Low-Power, Low-Latency DRAM With Built-in Cache
2017
Memory wall is a critical issue for many today’s electronic systems. Tiered latency DRAM with asymmetric bit lines was proposed to optimize the power and latency. This paper proposes a controller architecture for the tiered latency DRAM in which the small array is operated like a cache. —Jin-Fu Li, National Central University
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