A 34ns 16MbDRAM with controllable voltage down convertor

This practical 16MbDRAM has a RAS access time (tRAC) of 34ns and a column address access time (tCAA) of 15ns and provides high reliability by the retrograded well structure. Two circuit techniques are developed to meet high speed operation: multi divided address decoding, and fully embedded sense amplifier driving. Additionally two circuit innovations enhance the operating margin and reduce the power dissipation: twisted bitline with double dummy canceling and hybrid voltage down converter (VDC) with accelerative life-test function.