A novel self-aligned gate process for GaAs LSI using ECR-CVD

A novel substitutional self-aligned gate process for the GaAs LSI has been successfully developed utilizing ECR (electron cyclotron resonance) CVD (chemical vapor deposition). The high performance BP-LDD (BP-lightly doped drain) structure FET is obtained with sidewall formation and precise pattern reverse process using a photoresist dummy gate. A maximum transconductance of 440 mS/mm and a cutoff frequency of 39 GHz are obtained for a 0.45- mu m gate length FET. This new process is demonstrated by the preliminary fabrication of a 16-bit*16-bit E/D DCFL (enhancement/depletion directly coupled FET logic) multiplier using 0.65- mu m FETs with trilevel interconnection lines in which the top layer is an air bridge. A 4.3-ns multiplication time is observed at 5.5-W total power dissipation, which makes the fastest 16-bit*16-bit multiplier for GaAs MESFETs. >