Hardware and Power-Efficient Compression Technique Based on Discrete Tchebichef Transform for Neural Recording Microsystems

In this paper a new compression technique based on the discrete Tchebichef transform is presented. To comply with strict on-implant hardware implementation requirements, such as low power dissipation and small silicon area consumption, the discrete Tchebichef transform is modified and truncated. An algorithm is proposed to generate approximate transform matrices capable of truncation without suffering from destructive energy leakage among the coefficients. This is achieved by preserving orthogonality of the basis functions that convey majority portion of the signal energy. Based on the presented algorithm, a new truncated transformation matrix is proposed, which reduces the hardware complexity by up to 74% compared to that of the original transform. Hardware implementation of the proposed neural signal compression technique is prototyped using standard digital hardware. With pre-recorded neural signals as the input, compression rate of 26.15 is achieved while the root-mean-square of error is kept as low as 1.1%.Clinical Relevance— This paper proposes a technique for data compression in high-density neural recording brain implants, along with a power- and area-efficient hardware implementation. From among clinical applications of such implants one can point to neuro-prostheses, and brain-machine interfaces for therapeutic purposes.