An Automatic Temperature Compensation Of Internal Sense Ground For Sub-quarter Micron Drams

This paper describes DRAM array driving techniques and the parameter scaling techniques for a low voltage operation using the boosted sense ground (BSG) scheme andfurther improved methods. A temperature compensation and adjustable internal voltage levels maintain a small subthreshold leakage current of a memory cell transistor (MC-Tr), and a distributed BSG (DBSG) scheme and a column decoded sensing (CDS) scheme achieve the effective scaling. These schemes can set the DRAM array free from a leakage current problem and free them from an influence of temperature variations. Therefore, parameters for the MC-Tr, threshold voltage (V th ), and the boosted voltage for the gate bias can be scaled down, and it is possible to determine the V th of the MC-Tr easy (0.45 V at K = 0.4) for the satisfaction of the small leakage current, for the high speed and stable operation, and for the high reliability (V PP is below 2 V CC ). They are applicable to the subquarter micron DRAM's of 256 Mb and more