Development on ultra high density memory package with PoP structure

Memory package is expected with high density as much as possible for handheld devices, SSD & MP3…etc. However testing yield is always a challenge for multiple chip stacking. This paper presents a PoP (Package on Package) solution for high density memory package up to 16 chips. PoP has good advantage on flexibility and easy testing compare to 16 chips in one package but warpage control is more difficult especially for top and bottom package warpage matching. The test vehicle in this study is 8 chips BGA plus 8chips BGA with 32 Gb NAND. In order to keep low total package height, thin chip thickness (30um) and thin substrate thickness (100um) were applied. To optimize warpage level, a 3D Finite element simulation was performed to simulate the package warpage behavior and to study the material and structure effect. Both room temperature and reflow temperature were considered to check top and bottom packages waprage trend. The result showed package warpage is highly depends on structure and material properties. Based on the simulation result, a real top and bottom package of PoP were manufactured. And shadow moire test was performed to verify this design. Furthermore, moisture sensitivity test was performed to confirm the package reliability.