An 800 MS/s Dual-Residue Pipeline ADC in 40 nm CMOS

The 800MS/s 12b pipeline ADC presented here achieves a 59dB peak SNDR while consuming 105mW, resulting in an FOM of 0.18pJ/conversion-step. With digital power dissipation decreasing with technology much faster than analog power consumption, power efficient ADC designs have to make use of calibration. A major advantage offered by the dual-residue ADC architecture [1] is that the only calibration required is a calibration of the offset voltages of the MDAC amplifiers; a simple algorithm has been implemented that reaches convergence very rapidly and tracks the offsets for temperature drift and aging. Furthermore, the relaxed open-loop gain and bandwidth requirements of the MDACs allowed for a low-power implementation. Low power consumption is essential especially in applications where multiple high-speed ADCs have to be implemented on a single chip, such as 10GBase-T Ethernet.