Model for RHIC ramp controls

This paper introduces the hardware and software concepts for the implementation of the ramp controls. The hardware part of the ramp controls consists of a number of multi-purpose Wave Form Generators (WFGS) which control the settings of accelerator hardware directly or indirectly by controlling their WFG. A Real Time Data Link (RTDL) data transfer system connects the WFGs in a three layer architecture. To the usual two layers which generate an independent timing signal and dependent set points, respectively, an intermediate layer is added which produces accelerator parameters such as the magnet strength. The task of the bottom layer is therefore reduced to the function of implementing those parameters. This architecture de-couples two independent functions which axe normally folded together. The function of the hardware becomes modular and easily maintainable. The ramp control software is layered in the same way. Between the top layer (the ramp procedure application program) and the bottom layer (the hardware interface) an additional layer of ``manager`` programs allow operation of accelerator subsystems.