High Aspect Ratio Through-Wafer Interconnect for Three Dimensional Integrated Circuits

In this work, we examine deep silicon copper interconnect related failure mechanisms due to deep silicon via etching based on BOSCH process. Though it is the best candidate for performing deep and high aspect ratio silicon etching, its cyclical nature of doing series of etch and passivation process creates very rough sidewall thus impacting the electrical performance of through-wafer copper interconnection. In the present work we have designed a dedicated test vehicle to study and evaluate the deep silicon via etch induced defects such as sidewall scallops, conformality of dielectric isolation and copper diffusion barrier over the entire depth of the via. In addition, thermo-mechanical simulation has been done to identify the potential weak sites to help us to zoom into possible failures sites.