Evaluation and reduction of simulation error of chip-to-chip signal delay

This paper proposes an evaluation method of an error between measurement and simulation of chip-to-chip signal delay. It also presents a method to reduce the delay error in the simulation using IBIS model. In our example measurement and simulation by the proposed method, chip-to-chip delay error is 22 % (87ps) and delay errors in each segment (core logic cell, input/output buffer, package, board) are also obtained.