Interconnect layout macromodelling and simulation in high speed circuits

This paper deals with the layout problems of VHSICs. It shows how parasitic influence of the interconnects on the global circuit performance can be selectively taken into account. The method is based on the layout extraction coupled with a model library of basic forms. Hierarchical symbolic analysis is proposed to create macromodels and speed up the calculation. An example of 40 Gb/s driver design illustrates the presented approach.