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A 27% active-power-reduced 40-nm CMOS multimedia SoC with adaptive voltage scaling using distributed universal delay lines
A 27% active-power-reduced 40-nm CMOS multimedia SoC with adaptive voltage scaling using distributed universal delay lines
2011
Ikenaga
Nomura
Suenaga
Sonohara
Horikoshi
Saito
Ohdaira
Nishio
Iwashita
Satou
Nishida
Nose
Noguchi
Hayashi
Mizuno
Keywords:
Electronic engineering
CMOS
AC power
Computer science
Adaptive voltage scaling
Correction
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