Runtime mapping and scheduling for energy efficiency in heterogeneous multi-core systems

Heterogeneous Multi-core Processors (HMPs) have the potential to outperform homogeneous multi-core processors in terms of raw performance and/or energy as both their Instruction-Set Architectures (ISA) and cache configurations (size and set associativity) can be tailored to the specific needs of a computation. In this paper we describe algorithm for the generation of custom HMP and a dynamic run-time core-mapping and scheduling policy that exploits the heterogeneity of such systems customized with respect to the number of cores and L1 cache memory sizes. Experimental results targeting custom HMPs implemented on a contemporary Field-Programmable Gate Array (FPGA) with LEON3 cores as their base for a set of 50 application codes reveal that the proposed core-mapping and scheduling algorithms achieves an average execution time improvement of 18.3% and a 12% energy reduction over a static core-mapping and list-scheduling algorithms.