FPGA Implementation of A MIPS RISC Processor

This project targets the implementation design of a MIPS (Microprocessor without Interlocked Pipeline Stages) RISC (Reduced Instruction Set Computer) Processor using VHDL (Very high speed integrated circuit Hardware Description Language). In this paper MIPS instruction format, instruction data path, decoder modules are analyzed. Furthermore, we design instruction fetch (IF) module of a CPU based on RISC CPU instruction set. Function of IF module mainly includes fetch instruction and latch module address arithmetic module check validity of instruction module and synchronous control module.