Energy, Area, and Performance Evaluation

A detailed evaluation with respect to energy, area, and performance is important for a new processor architecture. However, comparing processor architectures is hard based on numbers in literature. There are various reasons to this: benchmarks are not the same, memories and their interfaces are often not taken into account, architectures are only functionally simulated, and energy numbers are either not mentioned, or it is not clear what is included in these numbers and what is left out. In order to provide a fair evaluation of Blocks against reference architectures (an SIMD, a VLIW, and a traditional CGRA), these architectures are implemented based on the function units supported by Blocks. By doing so, the instruction set architecture, ASIC technology node, memory arbitration, etc. are all comparable. Furthermore, Blocks is compared against an ARM Cortex-M0. All architectures are synthesized and placed and routed using a 40 nm low-power technology node. The results show that Blocks significantly reduces reconfiguration overhead even when compared to an already optimized, but more traditional, CGRA. Blocks reduces reconfiguration energy overhead between 46% and 76% (average 60%). The system level energy reduction is between 9% and 29% (average 22%). Despite reconfiguration overhead, energy consumption is 2.1× and 1.8× lower for Blocks when compared to the fixed SIMD and VLIW processors. Furthermore, Blocks energy is over 8× lower compared to an ARM Cortex-M0 while achieving a speed-up of 68.9×.