Exploiting power supply ramp rate for calibrating cell strength in SRAM PUFs

SRAM arrays are particularly attractive for use as physically unclonable functions (PUFs) because each manufactured copy of an SRAM array displays a different memory pattern when initially powered-on. This is due to random differences in device parameters in individual memory cells from manufacturing process variations. However, instability in the SRAM PUF response over the expected range of operating voltages and temperature, as well as environmental noise and aging degradation over time, is a challenge. Recent proposals aim at identifying a subset of all the cells in an SRAM, the most robust or strong cells, and using only these to construct a PUF. However, the manner in which the SRAM is powered up has been largely ignored in earlier work. We show that the SRAM power-up state is strongly dependent on the power supply ramp rate and direction; very different power-up states are obtained under different power-on scenarios. Furthermore, analyzing the power-up states under different ramp rates and directions can provide considerable insight into which transistor pairs in each individual cell are mismatched, and even the extent of the mismatch. Since such threshold voltage mismatch is key to cell power-on bias, we finally show how such experiments can be exploited to reliably identify the most robust strong cells in SRAMs for use in PUFs. These cells can be expected to generating reliable keys for cryptographic operations across a wide range of operating conditions, noise and device degradation.