30.8 A 0.65V 12-to-16GHz Sub-Sampling PLL with 56.4fs rms Integrated Jitter and -256.4dB FoM

Lowering supply voltage is an effective way to reduce circuit power consumption, especially in digital-centric system-on-chips (SoC). For low-jitter phase-locked loops (PLL) required in high-speed serial links and data converters, operation under low voltage is highly desirable such that the PLL can be readily integrated in a low-voltage (LV) SoC without a dedicated high-voltage supply. Among the various PLL architectures, the sub-sampling PLL (SSPLL) [1]–[3] offers low jitter with a superior jitter-power product figure-of-merit (FoM) because of its inherent rejection of N 2 amplification of in-band phase noise induced by the charge pump (CP) and phase detector (PD), as reported in [1]. However, the design of an LV SSPLL (LVSSPLL) must overcome several daunting issues. First, the CP design suffers from limited voltage headroom, degraded current noise, and limited output voltage range. Although the type-I SSPLL [3] can avoid this issue by eliminating the CP, it suffers from limited phase-noise suppression of the voltage-controlled oscillator (VCO). Second, the high on-resistance of the sub-sampling PD (SSPD) under low voltage causes attenuation of the sampled clock swing and thus degrades the in-band phase noise of the SSPLL induced by the SSPD.