CVD Cu Process Development and Integration for sub-0.18 µm Devices

The advent of inlaid Cu interconnects has presented new challenges for the industry to fill high aspect ratio dual inlaid features. CVD Cu offers advantages for excellent step coverage and is a technique extendible for future generations of devices. We have developed a robust CVD Cu process and a CVD/PVD reflow integration scheme. In this paper, we present results of an extensive study on CVD Cu process development and integration. The effects of various precursors, carrier gases (H2, He and N2) and barrier layers including CVD TiN, PVD Ta, PVD TaN, PVD Ta-Si-N, and a hybrid barrier, on the CVD Cu film properties and device electrical properties are discussed. The extendibility and challenges of current CVD Cu processing will also be discussed.