Research of Hardware Implementations Efficiency of Sorting Algorithms Created by Using Xilinx’s High-Level Synthesis Tool

The article describes results of our research of hardware implementation efficiency of sorting algorithms created by using of Xilinx’s High-Level Synthesis tools, the Vivado HLS package, and FPGAs. The term efficiency, used in the research, defined as a function of the performance, estimated in time for sorting a random generated array, and hardware “cost”, estimated in utilized FPGA resources. In the research, a simulation modeling and a comparative analysis was carried out for the wide range of sorting algorithms implemented on a universal processor and on the Xilinx’s FPGAs. The research results prove that hardware implementations of the sorting algorithms, synthesized by Xilinx HLS tool, do not always provide higher performance comparing with the implementations of the same algorithms on a universal processor. The article shows that the hardware implementation of the Merge sort algorithm, created by Xilinx’s HLS tool, can speed up, comparing with software implementation, the process of sorting arrays of small and medium size.