Total-dose-induced edge effect in SOI NMOS transistors with different layouts

The total-dose-induced edge effect in SOI NMOS transistors with different layouts is presented. Experimental results show that the edge effect is very sensitive to their layouts. Among the transistors hardened by design, the H-gate and ringed-source transistors do not behave as expected. At high radiation doses, the edge leakage currents appear for both transistors. Compared to the unhardened two-edged transistor, their total-dose-induced edge leakage paths and the role of layouts on edge effect are discussed.