A 0.25–1.0 V fully synthesizable three-stage dynamic voltage comparator based XOR&XNOR&NAND&NOR logic

To improve the performance of all-digital synthesizable comparators for the stochastic circuit, we present a three-stage rail-to-rail fully synthesizable dynamic voltage comparator. Compared with the state-of-the-art designs, the proposed comparator uses XOR, XNOR, NAND, and NOR logic gates to further improve the comparator’s common-mode input range, offset, speed and power-delay product (PDP). The comparator is implemented on CMOS 45 nm technology, operating with a supply voltage of 250 mV–1.0 V. The comparator has reduced the delay by 0.70 to $$0.82\times $$ , increased the standard deviation of offset by 1.28 to $$1.65\times $$ and reduced the PDP down to $$0.67\times $$ compared to NAND & NOR-based comparator. Hence, these improvements help to increase the performance of the stochastic Flash ADC, and improve the reliability of the stochastic PUF circuit.