Modeling of Self-Aligned Vertical ZnO Thin-Film Transistors

Vertical zinc oxide (ZnO) thin-film transistors (TFTs) with submicrometer channel length have good performance, including large current density (>10 mA/mm), high mobility (> 14 cm $^{2}$ /Vs), and large current ON–OFF ratio ( $>10^{7})$ . They also have asymmetric current–voltage ( $I$ – $V$ ) characteristics in the saturation region when the source and drain electrodes are interchanged. We have used 2-D simulations with the Synopsis Sentaurus Device to model vertical ZnO TFTs. The devices studied in this paper had ZnO active layers deposited using spatial atomic layer deposition (SALD). Model parameters were calibrated by matching simulation results with experimental results of planar bottom-gate ZnO TFTs and further adjusted to fit vertical TFT (VTFT) experimental characteristics. We find we need acceptor-like traps above and below the conduction band minimum to model the SALD ZnO semiconductor behavior; in this paper, we introduced these as bulk traps. We find the asymmetric $I$ – $V$ characteristics arise from an ungated region near the foot of the VTFT, and which has a more significant effect on charge injection than on charge extraction. Modeling TFTs with different ungated region lengths gave good agreement with experimental characteristics.