32-channel self-triggered ASIC for GEM detectors

Currently the multichannel readout chip for GEM detectors with an asynchronous architecture is being developed. The paper describes the 32-channel chip for GEMs and the test results of the chip building blocks. The chip includes the full readout channel with analog front-end and digital back-end. The channel includes a preamplifier with fast and slow CR-RC shapers, discriminator with a differential threshold setup circuit, an 8 bit SAR ADC (30 MSps rate, 1.5 mW power consumption), digital peak detector and block of the time stamp registration. The digital peak detector has a feature preventing the false peak detection. The chip version is considered to be compatible with the GBTx data processing board. Thus, the control data, clock and output data are supplied through SLVS transmitter and receiver. The slow and fast channels have 1000 e − and 1200 e − ENC (equivalent noise charge) accordingly at a 50 pF detector capacitance. Power consumption is 10 mW/channel.