A LAYOUT DRIVEN DESIGN FOR TESTABILITY TECHNIQUE FOR MOS VLSI CIRCUITS

Present design for testability techniques, in general, result in a large area overhead und perjormance clegruclation. An algorithm is presented which uses the layoul infornzation as well as the knowledge generated during the testgeneration process to select a set of observable lestpoints. These testpoints are implemented at the luyout level and suffer virtually no area and performance overhead. We have petjiormecl an experimentul evuluation of this technique where testpoints were inserted to sequentiul ISCAS-benchmarks and the fault coverage was obtained along with the urea and the performance overheads. The results show that our design for testubiliv method is cost effective and produces a high jault coverage for sequential circuits.