Integration of TmSiO/HfO 2 Dielectric Stack in Sub-nm EOT High- $k$ /Metal Gate CMOS Technology

Integration of a high- $k$ interfacial layer (IL) is a promising technological solution to improve the scalability of high- $k$ /metal gate CMOS technology. We have previously demonstrated a CMOS-compatible integration scheme for thulium silicate (TmSiO) IL and shown excellent characteristics in terms of equivalent oxide thickness (EOT), interface state density, channel mobility, and threshold voltage control. Here, we report on optimized annealing conditions leading to gate leakage current density comparable with state-of-the-art SiO x /HfO 2 nFETs (0.7 A/cm $^{2}$ at 1 V gate bias) at sub-nm EOT (as low as 0.6 nm), with near-symmetric threshold voltages (0.5 V for nFETs and −0.4 V for pFETs). We demonstrate an excellent performance benefit of the TmSiO/HfO 2 stack, i.e., improved channel mobility over SiO x /HfO 2 dielectric stacks, demonstrating high-field electron and hole mobility of 230 and 70 cm $^{2}$ /Vs, respectively, after forming gas anneal at EOT = 0.8 nm. Finally, the reliability of the TmSiO/HfO 2 /TiN gate stack is investigated, demonstrating 10-year expected lifetimes for both oxide integrity and threshold voltage stability at an operating voltage of 0.9 V.