Effects of the Device Parameters and Circuit Mismatches on the Static and Dynamic Behavior of Parallel Connections of Silicon Carbide MOSFETs

As a common practice into the use of silicon semiconductor devices, the capability of a discrete power switch may by augmented by using the parallel connection of several single MOSFETs. This paper deals with the main results of an experimental investigation about the issues linked to devices and circuit mismatches, regarding the parallel operations of Silicon Carbide (SiC) MOSFETs. Implementations into the state-of-the-art of paralleled SiC, which are used in switching converter, use discrete devices widely packaged as TO-220 or TO-247. In this case both the external and internal parasitic parameters have to be well bounded not to penalize the overall performance. Based on the experimental validation of paralleled discrete devices, this investigation firstly focuses on the main electrical parameters affecting the performance of the paralleled switches. Then, the influence of the circuit mismatch on paralleled SiC MOSFETs is investigated by selectively setting the value of the parameter under investigation (i.e. the external gate resistance, the drain stray inductances, the common source stray inductances). The impact of the “Kelvin source” connection, that is tailored to minimize the negative feedback of the source stray inductances into the voltage gate command, is also evaluated in terms of effects on the current unbalance mitigation, and about the power losses during the switching.