A 10-bit 300MHz 0.1mm 2 triple-channel current-steering DAC 75.98dB SFDR in 65nm

For this paper, we used the UMC 65 nm 1P10M CMOS logic process to design a 10-bit triple-channel current- steering DAC, which includes three channels of RGB. The analog/digital circuit was 2.5 V/1.2 V, the active area was 0.1 mm 2 per channel, and INL/DNL were each less than plusmn 0.4/plusmn 0.23LSB. We obtained an SFDR exceeding 75.98 dB while consuming only 6.24 mW of power per channel.