A 4-Gbps POF Receiver Using Linear Equalizer With Multi-Shunt-Shunt Feedbacks in 65-nm CMOS

This brief describes the design of a monolithic plastic optical fiber (POF) receiver with a pair of 250-by-250 μm N-well/P-sub photodetectors (PDs). A two-stage continuous-time linear equalizer that utilizes multiple active shunt-shunt feedback networks has been proposed to compensate for the slow-rolling-off high-frequency losses of the PDs. A test chip has been implemented in a standard 65-nm CMOS process, and it consists of a transimpedance amplifier, a variable-gain amplifier, a linear equalizer, a limiting amplifier, and an output buffer. The receiver consumes an active chip area of 0.24 mm 2 and a dc power of 46 mW (excluding auxiliary test circuits and the output buffer) from a 1-V power supply. The prototype POF receiver demonstrates a non-return-to-zero data rate of 4 Gbit/s with a bit error rate less than 10 -12 , at a peak-to-peak optical input power of - 3.2 dBm p-p (average input power is kept at -3 dBm).