Multilevel gold metallization

A process sequence for multilevel gold metallization of VLSI circuits has been developed. In this process, polyimide is used as an isolation layer. In order to minimize problems with planarization, the interconnections between metallization layers are made by gold pillars with completely fill the via holes. Plane conductor metallization levels are the results. The double-layer gold metallization process is presented, and the critical steps are discussed in detail. >