A WiSN node SoC with real-time image compressor and IEEE 802.15.4 MAC accelerator

This article presents a wireless image sensor node SoC (system-on-a-chip) for low-power wireless image sensor network (WiSN), in which camera chip interface, high-quality image compression and IEEE 802.15.4 compliant acceleration modules are integrated on chip. The proposed SoC contains a hardware-implemented real-time lossless JPEG (JPEG-LS) compression engine for Bayer Color Filter Arrays (Bayer CFA), reaching a 3.5 bits/pixel with peak signal to noise ratio (PSNR) greater than 46.3 dB and achieving a maximum 5 frames/s @16 MHz for VGA (640 × 480) colour images. The proposed hardware accelerator for IEEE 802.15.4 media access control (MAC) layer covers crucial protocol defined functions and algorithms, and reduces 45% software code in the host processor. This SoC has been fabricated in UMC 0.18 µm 1P6M CMOS process. The average power of the prototype chip is 18.2 mW at 3.0 V power supply and 16 MHz clock rate.