Area Efficient Double Edge Triggered Double Tail Comparator

Comparator is one of the main building blocks in most analog-to-digital converters. Many high speed analog- to-digital converters, such as flash ADCs, require high-speed, low power comparators with small chip area. In low power, area efficient, and high speed analog-to-digital converters we need dynamic regenerative comparators to increase speed and power efficiency. In this paper, a new dynamic comparator is proposed, where the circuit of a low voltage low power double tail comparator is modified for area efficient and double edge triggered operation. The simulated data presented is obtained using TANNER EDA tool with 180 nm technology. It is shown that in the proposed dynamic comparator both the power consumption delay time and are significantly reduced.