A PROGRAMMABLE 1-V CMOS 65 nm FREQUENCY SYNTHESIZER DESIGN IN 60 GHz WIRELESS TRANSCEIVER

The paper proposes a CMOS 65 nm 24 GHz wide-band frequency synthesizer with programmability on acquisition speed and supply voltage for low power application in 60 GHz millimeter-wave (mmW) wireless transceiver. The role of mmW phase-locked loop (PLL) is significant for supporting 7 GHz bandwidth across the four channels in IEEE 802.15.3c. The PLL is introduced with consideration of system specifications, as well as the design of individual block. In order to maintain the dynamic behavior of a PLL, two control parameters of its loop transfer function are used for programmability, including the charge pump current and pole-zero position. A regulator is also adopted for supply noise suppression. The Voltage-Controlled Oscillator (VCO) covers frequency range from 24.2 to 29.3 GHz, with 19.1% tuning range. On top of the oscillator, a 1.2 V LDO (Low-Dropout Regulator) with 0.2 V dropout voltage is introduced to increase the immunity against low frequency noise fluctuation from supply. With the proposed structure, the PLL provides a loop bandwidth from 0.94 to 2.05 MHz. The phase margin is larger than 54° and the locking time can be adjusted 16% faster than nominal case. The VCO has better power supply rejection ratio (PSRR) of -48 dB, and Phase Noise of -94 dBc/Hz at 1 MHz frequency offset of 24 GHz.