Scaling of high-kappa/metal-gate TriGate SOI nanowire transistors down to 10 nm width

Abstract In this paper, TriGate nanowire (TGNW) FETs with high-κ/metal gate are studied as an alternative way to planar devices for the future CMOS technological nodes (14 nm and beyond). The influence of Si film thickness ( H ) and nanowire width ( W ) on electrical performance of long- and short-channel devices are presented and discussed. We show that the transport properties in our TGNW are fully governed by the additive contributions of the (1 0 0) top surface and (1 1 0) sidewalls. As compared to wide planar devices, the improvement of electrostatic integrity (subthreshold slope and drain-induced-barrier-lowering) of scaled down TGNW FET is clearly demonstrated.