Determination of physical mechanism responsible for the capacitance-voltage weak inversion “hump” phenomenon in n-InGaAs based metal-oxide-semiconductor gate stacks

Weak inversion capacitance-voltage (C-V) “hump” is a widely observed phenomenon at n-InGaAs based metal oxide semiconductor (MOS) structures. The mechanism responsible for this phenomenon is still under discussion. The C-V hump can be explained as an interaction of interface states with either one or both semiconductor energy bands. Each of the proposed mechanisms leads to a different interpretation of C-V hump. Simulating the mechanisms by relevant equivalent circuits, the capacitance and conductance characteristics of the MOS structure were calculated and compared with experimental results. The mechanism responsible for the C-V hump was determined.Weak inversion capacitance-voltage (C-V) “hump” is a widely observed phenomenon at n-InGaAs based metal oxide semiconductor (MOS) structures. The mechanism responsible for this phenomenon is still under discussion. The C-V hump can be explained as an interaction of interface states with either one or both semiconductor energy bands. Each of the proposed mechanisms leads to a different interpretation of C-V hump. Simulating the mechanisms by relevant equivalent circuits, the capacitance and conductance characteristics of the MOS structure were calculated and compared with experimental results. The mechanism responsible for the C-V hump was determined.