(Invited) Cyclic Deposition/Etch Processes for the Formation of Si Raised Sources and Drains in Advanced MOSFETs

We have studied the Cyclic / Deposition Etch (CDE) of Si with either SiH4 or SiH2Cl2 + HCl for the deposition steps and HCl for the etch steps. The HCl etch rate of poly-Si is indeed several times higher than the one of mono-crystalline Si. We have demonstrated that at 650{degree sign}C, 300 Torr, SiH4 / HCl CDE processes were selective versus SiO2 for high numbers of cycles. We have also showed that 20 Torr, SiH2Cl2 + HCl - based CDE processes enabled to selectively grow 85 - 140 nm thick Si Raised S/Ds on each side of multi-bridge channel FETs with Si3N4 internal spacers. Finally, we have demonstrated the efficiency of various CDE process in suppressing mushrooming on top of un-capped poly-Si gates of FD-SOI FETs after the formation of Si RSD ({116} facets at the boundary between the gate stack and the S/D regions and moat recess, however).