Error Floor Compensation for LDPC Codes Using Concatenated Schemes

This paper quantitatively investigates the trade-offs in the compensation of error floor on iterative decoders. The characterization of iterative decoding systems prone to error floor at low noise is a great challenge as techniques based on software simulation are inadequate due to the extremely long simulation time required. We compare the BER performance as measured at very low BER using hardware accelerators and study the cost of compensation techniques in terms of hardware complexity and throughput. Specifically, techniques based on the use of diversity in LDPC decoders and the use of concatenated BCH-LDPC codes are considered and corresponding hardware optimizations are discussed. It is shown that an introduced synergy of error-floor compensation techniques achieves substantial coding gain up to 1 dB at low noise, not possible by conventional LDPC or BCH decoders. In addition, hardware reductions are achieved in the BCH subsystem, due to simple post-processing in the LDPC decoder.