An area-efficient 3.5GHz fractional-N frequency synthesizer with capacitor multiplier in millimeter-wave gigabit wireless communication

This paper presents a CMOS 65nm sigma-delta frequency synthesizer with an embedded capacitor multiplier to support the multi-gigabit baseband data rate for millimeter-wave wireless communication. The capacitor multiplier achieves an equivalent value of 540 pF and save 90 % of area for the main capacitor. It is optimized for noise performance to provide the phase noise of −117 dBc/Hz from voltage-controlled oscillator (VCO) at 1MHz frequency offset of 3.456 GHz. The current consumption for the multiplier is 327 uA. The VCO covers 3.5 GHz with 1GHz frequency range to supports multiple data rates (3.52 Gbps, 3.456 Gbps and 2.97 Gbps) in IEEE 802.15.3c. Moreover, a flexible reference frequency from 10 MHz to 40 MHz can be selected because of the feature given by fractional-N PLL architecture. The adjustable reference frequency therefore provides more design margin for system integration. With this area-efficient design, the synthesizer can be integrated into the 60GHz transceiver as a baseband solution.