Investigations on Pipeline Optimized Adaptive Fir Filter Architecture for Audio De-noising

This project proposes a high-speed retimed de-noising adaptive filter on different FPGA platforms using FIR filter. Retiming technique is the minimization of the clock period in a circuit. Using retiming, an adaptive filter can have a low critical path, low power consumption, and high throughput. In an adaptive filter, the least mean square (LMS) is the utmost familiar adaptive algorithm by virtue of its simple structure. LMS algorithm is easy to execute in the real-time systems; to improve its critical path, it is crucial to correct the LMS adaptive algorithm. The retimed VLSI architecture lifts up the operational speed of an adaptive filter through limiting the critical path using delay components and also has a faster convergence. A fine-grain pipelined LMS method is used to further increase the maximum operating speed which provides pipelining at a computational component level. The critical path delay in the Virtex-5 series FPGA platform for direct form implementation of retimed LMS is found to be 9.104 ns, whereas that of traditional un-retimed LMS structure is 24.283 ns, thereby minimization of 37% critical path delay is achieved. A fine-grain retimed adaptive filter on Virtex-5 series FPGA platform achieves 8% improvement in clock frequency compared to a retimed structure.