Interconnect Architecture of a Novel And-inverter Cone Based FPGA Cluster

With deep understanding of the characteristics of And-Inverter Cone (AIC), an alternative logic element for FPGA, a series of improvements are proposed to get an optimized interconnect architecture inside the logic cluster. The enhancements include removing the output crossbar, adopting Inverter-Suffixed Crossbar (ISC), optimizing the low load circuit path, dividing the feedback and output function, restricting the output level of AIC and removing the middle crossbar, mixing with the LUT element. An optimized architecture is derived through amounts of experiments. Compared to Stratix IV, Altera, the area of cluster is reduced by 9.06%.Implemented on the new AIC architecture, the average area-delay product of MCNC benchmarks are reduced by 40.82%; the average area-delay product of VTR benchmarks is reduced by 17.38%. Compared to the original AIC-based FPGA architecture, the area of AIC cluster is reduced by 23.16%. Implemented on the new AIC architecture, the average area-delay product of MCNC benchmarks are reduced by 27.15%; the average area-delay product of VTR benchmarks are reduced by 15.26%.