利用高介電係數電介質/金屬閘極結合化學氧化 物的整合結構去達到高效能的20奈米n型及p型 金屬氧化物半導體元件

In order to achieve the purpose of high performance metal-oxide-semiconductor (MOS) devices of 20-nm technology node, the dielectric material and gate length of MOS devices are must continuously thinning and scaling down. However, the gate leakage current density (Jg) is also enhanced by thinner thickness and worse insulation capability of gate dielectric. For this reason, high-K dielectric materials were introduced to reduce the gate leakage current density. Nevertheless, the flat band voltage (Vfb) and effective work function (EWF) of metal gate electrode are easily degraded to silicon middle band gap that induced by material intrinsic characteristic limit and high temperature activation steps. Consequently, the technology of higk-K dielectric/metal gate (MG) needs nonstop progress to overcome this issue. This dissertation is divided into four main parts to study the high-K-last/gate-last with the chemical oxide interfacial layer (IL) integration scheme, and this thesis focuses on the how to obtain high performance nMOS and pMOS devices of 20-nm technology node. In first investigate, this dissertation presents that the high-K-last/gate-last integration scheme involving the use of a thermal oxide interfacial layer (IL) could provide more thinner equivalent oxide thickness (EOT) than high-K first/gate-last with a thermal oxide integration scheme in 20-nm technology node. Even though, it is still difficult to further thin down EOT to meet the demand of high performance and low power for 20-nm technology node. This dissertation has proposed a high-K-last/gate-last integration scheme with a chemical oxide interfacial layer (IL) to meet EOT thin down requirement. It was found that chemical oxide IL could form Hf-silicate (HfSiO) element at the high-K/IL interface so as to provide us a larger effective K value and a smaller equivalent oxide thickness. It was also found that the larger gate leakage current density for the samples with chemical oxide IL could be effectively suppressed by post-deposition annealing (PDA)treatment. In another word, the PDA treatment was used to improve the performances of high-K-last/gate-last integration scheme with a chemical oxide IL. Furthermore, it was found that PDA treatment induced larger EOT could be reduced by optimizing the metal gate stack. It was also found that we could achieve small gate leakage current density and minimal flat-band voltage (Vfb) degradation of nMOS and pMOS devices by PDA treatment in O2 atmosphere. Furthermore, it was found that equivalent oxide thickness, gate leakage current density and flab-band voltage could be further improved by optimizing the metal gate stack. In order to further to thin down the EOT, this dissertation presents used a decoupled plasma nitridation (DPN) with post-nitridation annealing (PNA) treatment method to improve and enhance the performances of nMOS and pMOS devices with high-K-last/gate-last integration scheme and chemical oxide IL. By introducing N to form HfSiON, it was found that DPN with appropriate PNA treatments could provide smaller equivalent oxide thickness for both nMOS and pMOS devices. It was also found that we could achieve thebest overall device performance for the high-K-last/gate-last integration scheme with a chemical oxide IL by introducing lower percentage nitrogen gas content during DPN followed by higher temperature PNA. In last study, this dissertation propose the use of the atomic layer deposition (ALD) TiN barrier metal to replace the physical vapor deposition (PVD) TiN barrier meyal on high-K-last/gate-last pMOS devices with a chemical oxide interlayer in 20-nm technology node. And the Energy Dispersive Spectrometer (EDS) was used to analyze the element distributes of cross-section of metal gate electrode for verifying the ALD TiN barrier metal which could effectively suppress oxygen out-diffusion from the high-K/IL stack. It was found that the pMOS devices with ALD TiN barrier metal exhibit lower gate leakage current density and thinner equivalent oxide thickness. Furthermore, it was found that wecould achieve larger flat band voltage (Vfb) and larger equivalent work function (EWF) from the pMOS devices with ALD TiN barrier metal. It was also found that we could further improve the performances of the fabricated pMOS devices by increasing the ALD TiN thickness.