Cost-effective Ni-melt-FUSI boosting 32-nm node LSTP transistors

We demonstrated for the first time that novel Ni-FUSI process using FLA (Melt-FUSI) dramatically improved both electrical characteristics and cost-benefit performance of LSTP devices. Since the T inv was aggressively scaled (T inv = 2.1 nm) with keeping SiON-gate leakage current and increasing hole mobility twice, we achieved the record I on of 300 muA/mum at the I off of 20 pA/mum for the pMOS transistor with the L g of 45 nm at V d of -1.2 V.