Will SOI have a life for the low-power market?

We discuss key challenges for SOI CMOS to achieve sub-100 pA/m leakage current required for low-standby power applications. Recent 45 nm data is used to illustrate the importance of junction engineering to mitigate SOI floating body effect for low leakage design. With device scaling towards 22 nm node, both bulk and SOI technologies are expected to hit a fundamental GIDL limit. Extremely-thin body SOI provides a scaling path for low-leakage SOI. Finally, we identify several unique SOI opportunities that can broaden its appeal to the low power market.