Bias Generation and Calibration of CMOS Charge Qubits at 3.5 Kelvin in 22-nm FDSOI

In this paper, we propose a fully integrated area-efficient bias generation system using a single input reference for a 2D quantum core structure comprising quantum dot arrays. The arrangement of biases initializes the quantum structure before a sophisticated quantum experiment can commence. The circuit area is 0.011 mm2 and the power consumption is 220 µW at 3.5 K with a 0.8 V supply in a 22 nm FD-SOI process. The proposed scheme can be readily extended to more complex quantum structures.