Bipolar device design for high density high performance application

An analysis of a loaded ECL (emitter coupled logic) gate fabricated in a modern bipolar process shows that the delay is dominated equally by intrinsic and extrinsic components. The design of technology to minimize these components is discussed. As device dimensions are reduced the extrinsic delay components dominate; these components can be minimized by optimizing packing density and using reduced ECL voltage swings. It is suggested that circuits of complexity of 100 K gates and delays of less than 20 ps will be possible in the near future. >